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[
VHDL-FPGA-Verilog
]
VHDL-Clock
Description:
用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform:
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Size:
4096
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Author:
单单
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Search - epm7128 training board
Search - epm7128 training board